Memory cell with a stacked capacitor
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 27, 2001
Grant Date -
N/A
app pub date -
Sep 29, 1998
filing date -
Sep 29, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A semiconductor memory cell includes a field effect transistor coupled to a storage capacitor that formed as a multilayer stack over the surface of the silicon chip of the cell. The capacitor is formed by three conformal layers over the surface of a cup-shaped contact hole in a silicon oxide layer overlying the surface of the chip.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully