US Patent No: 6,207,558

Number of patents in Portfolio can not be more than 2000

Barrier applications for aluminum planarization

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Abstract

The present invention provides an effective barrier layer for improved via fill in high aspect ratio sub-micron apertures at low temperature, particularly at the contact level on a substrate. In one aspect of the invention, a feature is filled by first depositing a barrier layer onto a substrate having high aspect ratio contacts or vias formed thereon. The barrier layer is preferably comprised of Ta, TaN.sub.x, W, WN.sub.x, or combinations thereof. A CVD conformal metal layer is then deposited over the barrier layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal layer is deposited onto the previously formed CVD conformal metal layer at a temperature below that of the melting point temperature of the metal to allow flow of the CVD conformal layer and the PVD metal layer into the vias.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
APPLIED MATERIALS, INC.SANTA CLARA, CA6777

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ding, Peijun San Jose, CA 122 1536
Rengarajan, Suraj San Jose, CA 26 287
Singhvi, Shri Milpitas, CA 4 66
Yao, Gongda Fremont, CA 41 490

Cited Art

Patent Info (Count) # Cites Year
 
APPLIED MATERIALS, INC. (6)
4,951,601 Multi-chamber integrated process system 683 1989
5,028,565 Process for CVD deposition of tungsten layer on semiconductor wafer 120 1989
5,043,299 Process for selective deposition of tungsten on semiconductor wafer 79 1989
5,043,300 Single anneal step process for forming titanium silicide on semiconductor wafer 91 1990
5,250,467 Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer 57 1991
5,607,776 Article formed by in-situ cleaning a Ti target in a Ti+TiN coating process 22 1995
 
MICRON TECHNOLOGY, INC. (3)
5,032,233 Method for improving step coverage of a metallization layer on an integrated circuit by use of a high melting point metal as an anti-reflective coating during laser planarization 113 1990
5,147,819 Semiconductor metallization method 76 1991
5,240,739 Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers 77 1992
 
TEXAS INSTRUMENTS INCORPORATED (3)
4,920,072 Method of forming metal interconnects 38 1988
4,920,073 Selective silicidation process using a titanium nitride protective layer 57 1989
5,010,032 Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects 87 1989
 
AT&T BELL LABORATORIES (2)
5,102,827 Contact metallization of semiconductor integrated-circuit devices 23 1991
5,308,796 Fabrication of electronic devices by electroless plating of copper onto a metal silicide 59 1993
 
CORNELL RESEARCH FOUNDATION, INC. (2)
5,023,201 Selective deposition of tungsten on TiSi.sub.2 47 1990
5,439,731 Interconnect structures containing blocked segments to minimize stress migration and electromigration damage 72 1994
 
FUJITSU LIMITED (2)
4,985,750 Semiconductor device using copper metallization 106 1987
5,081,064 Method of forming electrical contact between interconnection layers located at different layer levels 35 1990
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
5,143,867 Method for depositing interconnection metallurgy using low temperature alloy processes 25 1991
5,585,673 Refractory metal capped low resistivity metal conductor lines and vias 103 1994
 
KABUSHIKI KAISHA TOSHIBA (2)
5,102,826 Method of manufacturing a semiconductor device having a silicide layer 24 1990
5,514,425 Method of forming a thin film 27 1995
 
MITSUBISHI DENKI KABUSHIKI KAISHA (2)
5,429,991 Method of forming thin film for semiconductor device 30 1993
5,480,836 Method of forming an interconnection structure 27 1994
 
MOTOROLA, INC. (2)
4,926,237 Device metallization, device and method 73 1988
4,994,410 Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process 115 1990
 
ADVANCED MICRO DEVICES, INC. (1)
4,960,732 Contact plug and interconnect employing a barrier lining and a backfilled conductor material 118 1989
 
BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM (1)
5,292,558 Process for metal deposition for microelectronic interconnections 65 1991
 
CANON KABUSHIKI KAISHA (1)
5,316,972 Process for forming deposited film by use of alkyl aluminum hydride and process for preparing semiconductor device 20 1992
 
FREESCALE SEMICONDUCTOR, INC. (1)
5,080,933 Selective deposition of polycrystalline silicon 33 1990
 
FUJITSU SEMICONDUCTOR LIMITED (1)
5,250,465 Method of manufacturing semiconductor devices 32 1992
 
INFINEON TECHNOLOGIES AG (1)
5,478,780 Method and apparatus for producing conductive layers or structures for VLSI circuits 35 1992
 
INMOS CORPORATION (1)
4,784,973 Semiconductor contact silicide/nitride process with control for silicide thickness 103 1987
 
NORTEL NETWORKS LIMITED (1)
5,354,712 Method for forming interconnect structures for integrated circuits 286 1992
 
ROUND ROCK RESEARCH, LLC (1)
5,384,284 Method to form a low resistant bond pad interconnect 100 1993
 
SGS-THOMSON MICROELECTRONICS, INC. (1)
5,585,308 Method for improved pre-metal planarization 54 1995
 
SHARP KABUSHIKI KAISHA (1)
5,312,774 Method for manufacturing a semiconductor device comprising titanium 30 1992
 
TOKYO ELECTRON LIMITED (1)
5,380,682 Wafer processing cluster tool batch preheating and degassing method 66 1993
 
U.S. PHILIPS CORPORATION (1)
5,106,781 Method of establishing an interconnection level on a semiconductor device having a high integration density 53 1990
 
ZIV, ALAN R. (57.5 PERCENT) (1)
4,938,996 Via filling by selective laser chemical vapor deposition 36 1988

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (22)
7,262,130 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals 7 2000
7,091,611 Multilevel copper interconnects with low-k dielectrics and air gaps 12 2002
7,105,914 Integrated circuit and seed layers 12 2002
7,378,737 Structures and methods to enhance copper metallization 2 2002
7,301,190 Structures and methods to enhance copper metallization 4 2002
6,743,716 Structures and methods to enhance copper metallization 10 2002
6,756,298 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals 55 2002
7,220,665 H.sub.2 plasma treatment 7 2003
7,067,421 Multilevel copper interconnect with double passivation 9 2003
6,995,470 Multilevel copper interconnects with low-k dielectrics and air gaps 4 2004
7,394,157 Integrated circuit and seed layers 4 2004
7,285,196 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals 7 2004
7,109,112 Method of providing a structure using self-aligned features 2 2004
7,262,505 Selective electroless-plated copper metallization 13 2004
7,253,521 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals 7 2004
7,504,674 Electronic apparatus having a core conductive structure within an insulating layer 2 2005
7,943,503 Trench interconnect structure and formation method 0 2006
7,402,516 Method for making integrated circuits 1 2006
7,535,103 Structures and methods to enhance copper metallization 2 2006
7,368,378 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals 2 2006
7,670,469 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals 0 2007
7,745,934 Integrated circuit and seed layers 0 2008
 
SAMSUNG ELECTRONICS CO., LTD. (3)
6,413,853 Method of forming a tungsten plug in a semiconductor device 2 2001
6,905,960 Method of forming a contact in a semiconductor device 1 2003
7,189,641 Methods of fabricating tungsten contacts with tungsten nitride barrier layers in semiconductor devices, tungsten contacts with tungsten nitride barrier layers 0 2004
 
APPLIED MATERIALS, INC. (2)
6,528,180 Liner materials 2 2000
7,550,055 Elastomer bonding of large area sputtering target 2 2005
 
LEXMARK INTERNATIONAL, INC. (2)
6,794,753 Diffusion barrier and method therefor 1 2002
6,887,782 Diffusion barrier and method therefor 2 2004
 
GLOBALFOUNDRIES INC. (1)
8,404,577 Semiconductor device having a grain orientation layer 0 2008
 
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (1)
6,492,268 Method of forming a copper wiring in a semiconductor device 7 2000
 
NEC ELECTRONICS CORPORATION (1)
6,391,774 Fabrication process of semiconductor device 7 2000
 
PROMOS TECHNOLOGIES INC. (1)
6,413,384 Method for maintaining the cleanness of a vacuum chamber of a physical vapor deposition system 2 2000
 
RENESAS ELECTRONICS CORPORATION (1)
6,872,653 Manufacturing method of semiconductor device 1 2003
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
6,342,448 Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process 81 2000
 
TOKYO ELECTRON LIMITED (1)
6,508,199 Plasma processing apparatus 8 2000