Semiconductor memory device having resistive bitline contact testing
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United States of America Patent
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Mar 27, 2001
Grant Date -
N/A
app pub date -
Jun 12, 2000
filing date -
Jun 12, 2000
priority date (Note) -
Expired
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Abstract
A semiconductor memory device having resistive bitline contact testing includes memory cells, and wordline logic devices for concurrently activating two adjacent memory cells. The two adjacent memory cells are activated concurrently to allow higher current through a bitline contact for improved detection of resistive bitline contacts. A test cell may also be included to test the integrity of the bitline contact.
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