Reliable interrupt reception over buffered bus
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United States of America Patent
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Mar 27, 2001
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N/A
app pub date -
Dec 15, 1998
filing date -
Dec 15, 1998
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Abstract
A method and apparatus for reliable interrupt reception over a buffered bus utilizes a non-delayed non-posted write transaction to write data over the bus from a peripheral device to host memory. Because there is no buffering delay in a non-delayed non-posted write transaction, at the completion of the write cycle the peripheral knows that the write transaction is complete and then sends an interrupt request to the host processor requesting the host processor to service the interrupt and process the contents of the host memory.
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