Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
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United States of America Patent
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Mar 27, 2001
Grant Date -
N/A
app pub date -
Nov 1, 1996
filing date -
Nov 1, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method of automatically placing transistors of a folded transistor circuit for synthesizing rows of transistors in a semiconductor layout (172). First, an initial placement of transistors is generated (802). Next, a candidate move of transistors is selected (804). Then the change in cost of the placement resulting from applying the candidate move is evaluated (806). A decision is made to accept the candidate move based on the evaluation of its cost (808). If accepted, the move is performed (810) and the cost of the placement is updated (812). Finally, a decision to terminate the process is made (814).
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