Method for analyzing probe yield sensitivities to IC design
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United States of America Patent
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Apr 3, 2001
Grant Date -
N/A
app pub date -
Jun 15, 1999
filing date -
Oct 21, 1998
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Abstract
A method for predicting yield limits of semiconductor wafers in a factory, including the steps of generating a wafer probe test pareto, determining a histogram of the distribution from a selected group from the wafer probe test pareto, extracting parametric data from a database from the histogram, screening the parametric data for values of the parametric data outside of a predetermined range, determining if an average value of the screened parametric data shows a sensitivity to variations in the parametric data, determining specification limits of the screened parametric data, and using the specification limits to form an operating window to show the sensitivity.
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