FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections
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United States of America Patent
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-
Apr 3, 2001
Grant Date -
N/A
app pub date -
Jan 21, 1999
filing date -
Jan 21, 1999
priority date (Note) -
Reissued
status (Latency Note)
Importance
Abstract
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has a registered address port for capturing received address signals in response to further-received, address-validating clock signals. Interconnect resources are provided for conveying the address-validating clock signals to address-changing circuitry so that a next address can be generated safely in conjunction with the capturing by the registered address port of a previous address signal.
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