Clock and data recovery PLL based on parallel architecture
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United States of America Patent
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Apr 3, 2001
Grant Date -
N/A
app pub date -
Apr 29, 1999
filing date -
Oct 16, 1998
priority date (Note) -
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Abstract
An apparatus comprising a first circuit and a clock circuit. The first circuit may be configured to generate an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal. The clock circuit may be configured to generate the first and second clock signals in response to the output signal.
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