Methods and apparatus for handling and storing bi-endian words in a floating-point processor
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United States of America Patent
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Apr 3, 2001
Grant Date -
N/A
app pub date -
Oct 10, 1998
filing date -
Oct 10, 1998
priority date (Note) -
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Abstract
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
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