Method of fabricating a multi-chip module
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United States of America Patent
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Apr 10, 2001
Grant Date -
N/A
app pub date -
Nov 23, 1999
filing date -
Jun 25, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A lead-over-chip single-in-line memory module (LOC SIMM) and method of manufacturing is disclosed that provides for shortened wire bonds and ease of rework for unacceptable semiconductor dice. More specifically, the LOC SIMM of the present invention includes a plurality of slots extending through a circuit board with an equal number of semiconductor dice attached thereto such that the active surfaces of the dice are exposed through the slots. Wire bonds or TAB connections are made from the exposed active surface of the die, through the slot, and to contacts on the top surface of the circuit board. Dice proven unacceptable during burn-in and electrical testing of the module are replaced by known good dice (KGD) by breaking their respective wire bonds, attaching a KGD to the circuit board, and forming new electrical connections between the KGD and the circuit board.
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