Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system
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United States of America Patent
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Apr 10, 2001
Grant Date -
N/A
app pub date -
Aug 12, 1998
filing date -
Aug 12, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A graphics sub-system having a 2-D graphics accelerator, a 3-D graphics accelerator and an embedded DRAM memory. The embedded DRAM memory serves as a frame buffer memory and/or a temporary storage memory for the 2-D graphics accelerator. The embedded DRAM memory also serves as a cache memory for the 3-D graphics accelerator or an external central processing unit (CPU). The embedded DRAM memory is logically divided into a plurality of independent banks, thereby resulting in a relatively fast average memory cycle time. More specifically, the embedded DRAM memory processes one transaction per clock cycle for accesses with no bank conflicts. The memory access time for any transaction (e.g., a bank-conflict access) is no greater than the memory cycle time plus the memory access time minus 1 clock cycle.
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