Nonvolatile memory cell structure for integration with semiconductor logic devices and method of using same
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United States of America Patent
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Apr 10, 2001
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N/A
app pub date -
Dec 22, 1998
filing date -
Dec 22, 1998
priority date (Note) -
Expired
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Abstract
A nonvolatile memory cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors provides a floating gate for storing data while the other transistor is provided with a control gate for selecting the memory cell, and is connected with a bit line for reading data stored in the cell. The nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the nonvolatile memory cell may be fabricated in a logic device with the standard processes used to produce the logic device.
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