Test system and methodology to improve stacked NAND gate based critical path performance and reliability
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United States of America Patent
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Apr 10, 2001
Grant Date -
N/A
app pub date -
Sep 5, 1997
filing date -
Sep 5, 1997
priority date (Note) -
Expired
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Abstract
A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data. The reliability data is used to calibrate an aged transistor model, which describes the hot carrier reliability of sub-minimum channel length transistors. A computer simulation uses the calibrated, aged transistor model to simulate the critical path circuitry including the stacked NAND gates.
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