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Abstract

An address queue in a processor having the capability to track memory-dependencies of memory-access instructions is disclosed. The queue includes a first matrix of RAM cells that tracks a first dependency relationship between a plurality of instructions based upon matching virtual addresses (that identify a common cache set) and the order of instructions in the queue. To facilitate out-of-order instruction execution, dependencies may be tracked before virtual addresses are actually calculated based upon a presumption of dependency. Such dependency is dynamically corrected as addresses become available. The same comparison mechanism used to determine matching virtual addresses for the dependency relationship may also be used to read status bits of a cache set being accessed. The queue also includes a second matrix of RAM cells that tracks a second dependency relationship between a plurality of instructions based upon matching virtual addresses (that identify a common cache set, common doubleword and overlapping byte), the order of instructions in the queue and instruction type. Also disclosed is a method for processing memory instructions that uses a single comparison step between first and second virtual addresses (calculated from instructions) to indicate a dependency relationship between the instructions and to read memory status bits. The status bits are read to determine accessibility of a way within an addressed cache set.

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First Claim