Microprocessor circuits, systems, and methods implementing a load target buffer with entries relating to prefetch desirability
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 10, 2001
Grant Date -
N/A
app pub date -
Dec 30, 1997
filing date -
Dec 31, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A microprocessor (12) comprising a memory system (20) for outputting data in response to an address, wherein the memory system is further operable to receive a prefetch request having a predicted target data address. The microprocessor further includes a load target circuit (56 or 112), which comprises a first plurality of entries (116) of a first length and a second plurality of entries (114) of a second length. Each of the first plurality of entries comprises a value (ADDRESS TAG) for corresponding the entry to a corresponding first plurality of data fetching instructions. Further, each of the first plurality of entries further comprises a value (POINTER A) for indicating a corresponding predicted target data address. Each of the second plurality of entries also comprises a value (ADDRESS TAG) for corresponding each of the second plurality of entries to a corresponding second plurality of data fetching instructions. However, each of the second plurality of data fetching instructions is of a type for which it is undesirable to issue a prefetch request.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully