Integrated circuit design using a frequency synthesizer that automatically ensures testability
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United States of America Patent
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Apr 10, 2001
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N/A
app pub date -
Dec 16, 1998
filing date -
Dec 16, 1998
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Abstract
A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow the integrated circuit to operate in a system mode for normal function and in a test mode during testing. In the test mode, the testability circuit will inhibit the reset signal from initializing the integrated circuit until the frequency synthesizer has reached phase lock. The testability circuit may be implemented as a component in the frequency synthesizer cell in an ASIC design system such that anytime the frequency synthesizer is used, the integrated circuit is testable.
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