Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk
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United States of America Patent
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Apr 17, 2001
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N/A
app pub date -
Jul 14, 1998
filing date -
May 13, 1998
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Abstract
A structure for reducing cross-talk in VLSI circuits is disclosed. By filling voltage and ground metal lines in free or unused channels of VLSI chips and connecting them efficiently to the regular power image of the chip, the line to line coupling through vertical layers is reduced almost to zero and in-layer line to line coupling is also drastically reduced.
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