High speed programmable logic architecture
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United States of America Patent
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-
Apr 17, 2001
Grant Date -
N/A
app pub date -
Oct 11, 1996
filing date -
Jan 27, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. Instead of employing passive circuit elements to interconnect the programmable logic elements and the input and output data buses, controllable active driver circuits are employed. These circuits eliminate essentially all of the resistance present in prior art passive connections.
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