Method for eliminating stress induced dislocations in CMOS devices

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6221735
SERIAL NO

09504991

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The stress dislocations formed in a substrate by semiconductor processing are significantly reduced, if not eliminated, by subjecting the substrate to a high temperature post sacrificial oxide anneal that causes viscous flow of the oxide over the substrate. In one example embodiment, a method of forming a semiconductor structure includes forming a first oxide layer over a substrate and forming a first dielectric material layer over the first oxide layer. An opening is then etched in the oxide and dielectric layers thereby exposing the substrate. A trench is formed with a desired depth in the substrate in the opening provided, followed by a deposition of an insulator material in the trench. The first dielectric layer and a portion of the insulator material is then removed leaving a portion of the insulator material within the trench. Applications include logic circuits having embedded-DRAM and circuits directed to stand-alone logic or stand-alone DRAM.

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Patent Owner(s)

Patent OwnerAddress
INVENSAS CORPORATION2702 ORCHARD PARKWAY SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Manley, Martin Saratoga, CA 3 219
Nouri, Faran Los Altos, CA 18 441

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