Importance

Loading Importance Indicators...

Abstract

In one embodiment, a multistage output buffer supplies current to a load by successively turning ON output buffer circuits which transition from an OFF state to approximately a saturated state during approximately mutually exclusive periods of time. Thus, the aggregate dI/dt of the contributed by the output buffer drivers is primarily associated with a single output buffer driver. Additionally, the respective output driver transition periods are controlled by delay stage impedance to reduce dI/dt. The consecutive activation of the output buffer drivers may be achieved by using respective delay stages to control activation of associated, respective output buffer drivers. Each delay stage receives a delayed output control signal from a previous delay stage, except for the first delay stage which receives a control input signal from a signal source. Each delay stage also delays activation of its own output control signal with delay circuit elements such as relatively HIGH impedance IGFETs. The output control signals from each delay stage relatively slowly charge a gate of the associated, respective output buffer driver to activate the output buffer driver and cause a successive delay stage to begin activating the respective output control signal of the successive delay stage. In this manner, each delay stage and, thus, each associated, respective output buffer driver depends on the previous delay stage output control signal to begin the state transition of the respective output buffer driver. Furthermore, the number of delay stages to be activated is programmable to conserve power and further decrease dI/dt induced noise.

Loading the Abstract Image...

First Claim