Method and apparatus for evaluating software programs for semiconductor circuits
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United States of America Patent
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Apr 24, 2001
Grant Date -
N/A
app pub date -
Mar 24, 1998
filing date -
Mar 24, 1998
priority date (Note) -
Expired
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Abstract
A microcontroller software testing tool is disclosed for testing and debugging software for a semiconductor circuit. The microcontroller software testing tool includes a simulator for simulating the execution of the software program on the target semiconductor circuit and an emulator to permit emulation before the actual silicon exists. The emulator utilizes the same high definition language specification, such as VHDL models, that define the silicon during the fabrication process plus additional logic to model behavior of the emulated processor. In a simulation mode, the microcontroller software testing tool simulates the target semiconductor circuit on a general purpose computing device, by interpreting the instructions in the software using an instruction set of the target semiconductor circuit, and otherwise behaving like the target semiconductor circuit; and executes and evaluates the software on the simulated semiconductor circuit. The microcontroller software testing tool monitors the estimated time to execute the software on the semiconductor circuit. In an emulation mode, the microcontroller software testing tool utilizes a low-cost field programmable gate array programmed with a hardware description language description of the target semiconductor circuit. The microcontroller software testing tool is accessible by means of a data exchange protocol provided by the operating system. The microcontroller software testing tool preferably provides a modular configuration. The microcontroller software testing tool monitors the percentage of the code that is executed during testing.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- SILICON STORAGE TECHNOLOGY, INC.
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Barnett, Philip | Clanfield, GB | 2 | 108 |
Green, Andy | North Ants, GB | 12 | 119 |
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Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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