Importance

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Abstract

A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ('AGP') bus and host and memory buses, or as a bridge between a system area network interface and the host bus and the system memory bus. The function of the multiple use chipset is determined at the time of manufacture of the computer system, or in the field whether an AGP bus bridge or a system area network interface is to be implemented. Selection of the type of bus bridge (AGP or system area network interface) in the multiple use core logic chipset may be implemented by a hardware signal input, or by software during computer system configuration or power on self test ('POST'). Software configuration may also be determined upon detection of either an AGP device or a system area network interface connected to the core logic chipset.

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First Claim