US Patent No: 6,223,260

Number of patents in Portfolio can not be more than 2000

Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states

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Importance

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Abstract

A data processing system is comprised of: a system bus having a main memory coupled thereto; multiple high level cache memories, each of which has a first port coupled to said system bus and a second port coupled to a respective processor bus; and each processor bus being coupled through respective low level cache memories to respective digital computers. In the high level cache memories, data words are stored with respective tag bits which identify each data word as being stored in one of only four states which are shared, modified, invalid, or exclusive. In the low level cache memories, data words are stored with respective tag bits which identify each data word as being stored in only one of three states which are shared, modified or invalid.

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First Claim

Related Publications

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Patent Owner(s)

Patent OwnerAddressTotal Patents
UNISYS CORPORATIONBLUE BELL, PA2757

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Castle, David Edgar Poway, CA 4 84
Flora, Laurence Paul Valley Center, CA 2 43
Gujral, Manoj Santa Clara, CA 12 127
Sassone, Brian Joseph Los Gatos, CA 1 40

Cited Art

Patent Info (Count) # Cites Year
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (4)
5,136,700 Apparatus and method for reducing interference in two-level cache memories 58 1989
5,432,918 Method and apparatus for ordering read and write operations using conflict bits in a write queue 138 1992
5,285,323 Integrated circuit chip having primary and secondary random access memories for a hierarchical cache 51 1993
5,297,269 Cache coherency protocol for multi processor computer system 171 1993
 
SUN MICROSYSTEMS, INC. (3)
4,755,930 Hierarchical cache memory system and method 163 1985
5,398,325 Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems 71 1992
5,581,729 Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system 77 1995
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
5,623,632 System and method for improving multilevel cache performance in a multiprocessing system 25 1995
5,706,464 Method and system for achieving atomic memory references in a multilevel cache data processing system 28 1996
 
NEC CORPORATION (2)
5,274,790 Cache memory apparatus having a plurality of accessibility ports 53 1991
5,581,725 Cache memory system having first and second direct-mapped cache memories organized in hierarchical structure 26 1993
 
SGS-THOMSON MICROELECTRONICS, INC. (2)
5,319,768 Control circuit for resetting a snoop valid bit in a dual port cache tag memory 19 1991
5,513,335 Cache tag memory having first and second single-port arrays and a dual-port array 34 1992
 
BENCHMARQ MICROELECTRONICS, INC. (1)
5,249,282 Integrated cache memory system with primary and secondary cache memories 105 1990
 
BULL HN INFORMATION SYSTEMS INC. (1)
5,394,555 Multi-node cluster computer system incorporating an external coherency unit at each node to insure integrity of information stored in a shared, distributed memory 190 1992
 
CVSI, INC. (1)
5,113,514 System bus for multiprocessor computer system 67 1990
 
FREESCALE SEMICONDUCTOR, INC. (1)
5,598,550 Cache controller for processing simultaneous cache accesses 25 1994
 
INTEL CORPORATION (1)
5,522,057 Hybrid write back/write through cache having a streamlined four state cache coherency protocol for uniprocessor computer systems 22 1993
 
KABUSHIKI KAISHA TOSHIBA (1)
5,241,641 Hierarchical cache memory apparatus 40 1990
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
5,465,344 Microprocessor with dual-port cache memory for reducing penalty of consecutive memory address accesses 20 1994
 
UNISYS CORPORATION (1)
5,539,893 Multi-level memory and methods for allocating data most likely to be used to the fastest memory level 27 1993

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
JUNIPER NETWORKS, INC. (34)
7,908,472 Secure sockets layer cut through architecture 0 2001
7,853,781 Load balancing secure sockets layer accelerator 1 2001
7,228,412 Bufferless secure sockets layer architecture 14 2001
7,149,892 Secure sockets layer proxy architecture 29 2001
7,082,464 Network management system 56 2001
7,068,603 Cross-bar switch 2 2001
6,839,808 Processing cluster having multiple compute engines and shared tier one caches 13 2001
7,184,446 Cross-bar switch employing a multiple entry point FIFO 8 2001
7,170,902 Cross-bar switch incorporating a sink port with retry capability 2 2001
7,123,585 Cross-bar switch with bandwidth allocation 2 2001
7,103,058 Cross-bar switch with explicit multicast support 3 2001
7,082,139 Cross-bar switch with sink port accepting multiple packets 2 2001
7,065,090 Cross-bar switch supporting implicit multicast addressing 3 2001
6,938,093 Bandwidth allocation for a data path 1 2002
6,920,529 Transferring data between cache memory and a media access controller 0 2002
6,920,542 Application processing employing a coprocessor 1 2002
6,901,488 Compute engine employing a coprocessor 1 2002
6,901,489 Streaming input engine facilitating data transfers between application engines and memory 2 2002
6,898,673 Co-processor including a media access controller 0 2002
6,895,477 Ring-based memory requests in a shared memory multi-processor 15 2002
6,892,282 Ring based multi-processing system 12 2002
6,880,049 Sharing a second tier cache memory in a multi-processor 18 2002
6,862,669 First tier cache memory preventing stale data storage 0 2002
6,754,774 Streaming output engine facilitating data transfers between application engines and memory 19 2002
6,745,289 Processing packets in cache memory 9 2002
7,363,353 Content service aggregation device for a data center 18 2002
7,305,492 Content service aggregation system 35 2002
7,827,404 Secure sockets layer proxy architecture 0 2006
7,813,364 Cross-bar switch incorporating a sink port with retry capability 0 2006
7,733,905 Cross-bar switch having bandwidth allocation 0 2007
8,266,264 Launching service applications using a virtual network management system 0 2007
8,284,664 Redirecting data units to service modules based on service tags and a redirection table 0 2007
7,765,328 Content service aggregation system 7 2007
8,370,528 Content service aggregation system 0 2010
 
INTEL CORPORATION (3)
6,591,341 Multilevel cache system and method having a merged tag array to store tags for multiple data arrays 7 2000
7,546,422 Method and apparatus for the synchronization of distributed caches 0 2002
6,836,826 Multilevel cache system and method having a merged tag array to store tags for multiple data arrays 2 2003
 
INTELLECTUAL VENTURES FUND 35 LLC (1)
6,874,068 Shared memory 0 2000
 
NEXSI SYSTEMS CORPORATION (1)
7,200,662 Integrated rule network management system 10 2002
 
NEXSI SYSTEMS, INC. (1)
6,901,482 Managing ownership of a full cache line using a store-create operation 14 2002