Test vector verification system

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United States of America Patent

PATENT NO 6223272
SERIAL NO

09116062

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Abstract

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The present invention relates to a verification system for verifying whether vector outputs from a software simulator match the vector outputs from a hardware emulator by comparing a pair of checksums. A first checksum value is calculated from the output vectors obtained from the software simulator and a second checksum is calculated from the output vectors obtained from the hardware emulator. Accordingly, only a checksum value is required to be downloaded or uploaded, thereby eliminating the need to upload or download large numbers of output vectors. The system includes a software simulator for generating a set of input and output vectors, a checksum calculator for calculating the checksum of the output vector generated by the software simulator, a hardware emulator for receiving and storing the vector inputs and the checksum value generated by the software simulator and for generating output vectors based on the downloaded input vectors, a checksum calculator for calculating the checksum of the vector outputs generated by the hardware emulator and a checksum comparator for comparing the checksums.

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Patent Owner(s)

Patent OwnerAddress
INFINEON TECHNOLOGIES AGGERMAN NOE BE BERG NEUBIBERG BAVARIA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Coehlo, Paul R Sunnyvale, CA 1 73
Fu, Yeh-Chen Sunnyvale, CA 1 73
Gautho, Manuel O San Jose, CA 2 74

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