Importance

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Abstract

A circuit for controlling execution of a loop in a digital signal processing chip. The circuit includes a least significant bit state detection unit to output an effective signal of a predetermined level according to the state of a least significant bit and the states of first and second signals, when every bit other than the least significant bit is zero as a result of detection of the state of each bit in a counter register to which the number of loop executions is loaded; a conditional clock output unit to receive a clock signal and the first and second signals and output the clock signal only when the first or second signal is effective; and an ending condition signal output unit to output the output signal of the least significant bit state detection unit when a signal output from the conditional clock output unit is effective. Therefore, the circuit can prevent an error from being generated when the number of loop executions is zero, reduce the execution time upon realization of an entire algorithm, and prevent waste of a program memory.

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First Claim