Fault tolerant memory
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United States of America Patent
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Apr 24, 2001
Grant Date -
N/A
app pub date -
Sep 30, 1997
filing date -
Sep 30, 1997
priority date (Note) -
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Abstract
A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.
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