Method and apparatus for settling and maintaining a DC offset
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United States of America Patent
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May 1, 2001
Grant Date -
N/A
app pub date -
Feb 29, 2000
filing date -
Apr 13, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
A DC offset correction loop (200) utilizes a sign bit generator (204), binary search stage (206), and a digital-to-analog converter (208) in its feedback path to correct for DC offsets at the input of a gain stage (202). When a correction value is obtained, it is applied and held (524) to compensate for the DC offset. When a programming event occurs (534), such as detecting an increase in DC offset beyond a threshold, detecting a significant temperature change, or passage of time, a new DC offset correction cycle is initiated.
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