Semiconductor memory
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United States of America Patent
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May 8, 2001
Grant Date -
N/A
app pub date -
Apr 26, 2000
filing date -
Apr 28, 1999
priority date (Note) -
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Abstract
A semiconductor memory in accordance with the present invention includes a sense amplifier composed of a plurality of MOS transistors. When the sense amplifier is on standby, a first control circuit brings an input signal of the sense amplifier to zero. A second control circuit uses voltages developed because of an offset voltage occurring in the sense amplifier to feed back the potentials in the wells of the MOS transistors so that the offset voltage will be nullified. When the offset voltage occurring in the sense amplifier is nullified, a delay time required by the sense amplifier is shortened. This results in the high-speed semiconductor memory.
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