Reducing waiting time jitter
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United States of America Patent
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May 8, 2001
Grant Date -
N/A
app pub date -
Nov 2, 1998
filing date -
Nov 2, 1998
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a 'sub-bit' comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term 'sub-bit' means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.
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