Method and apparatus for extracting and storing connectivity and geometrical data for a deep sub-micron integrated circuit design
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United States of America Patent
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May 8, 2001
Grant Date -
N/A
app pub date -
Mar 31, 1998
filing date -
Mar 31, 1998
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A data extraction tool is provided to extract filtered connectivity and geometrical data for specified layout cell hierarchies of an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The connectivity and geometrical data for each layout cell hierarchy are extracted at least in part in accordance with specified parasitic effect windows. In one embodiment, the data extraction tool includes a filtered extraction function that operates to extract connectivity and geometrical data for layout nets of each layout cell hierarchy of the IC design, one or more layout nets at a time. Additionally, one or more filtered databases are provided to store the filtered connectivity and geometrical data of the layout cell hierarchies.
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