Method and apparatus for minimization of process defects while routing
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United States of America Patent
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May 8, 2001
Grant Date -
N/A
app pub date -
Apr 17, 1998
filing date -
Apr 17, 1998
priority date (Note) -
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Abstract
A method for optimizing the routing of nets in an integrated circuit device, said method comprising the steps of dividing an integrated circuit design with lines in a first direction and lines in a second direction, wherein said first direction is substantially orthogonal to said second direction, forming a routing graph with vertices corresponding to locations where lines in said first direction and lines in said second direction cross and edges connect vertices, for each edge in a plurality of edges in said routing graph, computing an individual edge occupancy value, for an edge in said plurality of edges, computing a penalty value as a function of the individual edge occupancy value of a different edge, and routing a net as a function of said penalty value.
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