Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
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United States of America Patent
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May 15, 2001
Grant Date -
N/A
app pub date -
Apr 28, 1998
filing date -
May 19, 1994
priority date (Note) -
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Abstract
A method of manufacturing a plurality of semiconductor chips packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A spacer layer is deposited or attached to the substrate and each chip is then attached to the spacer layer. The leads interconnect contacts on the chip to the terminals on the substrate wherein at least some of the terminals lie outside the periphery of the chip. Typically, the spacer layer is comprised of a compliant or resilient material. A curable encapsulant material is deposited so as to encapsulate the leads and at least one surface of the chip. A unitary support structure is then aligned and attached to the encapsulant around the edges of the chips. The encapsulant material is then cured thereby defining a composite of chip assemblies which may be singulated into individual chip packages.
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