
US Patent No: 6,232,217
Number of patents in Portfolio can not be more than 2000
Post treatment of via opening by N-containing plasma or H-containing plasma for elimination of fluorine species in the FSG near the surfaces of the via opening
Stats
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May 15, 2001
Issued date -
Jun 5, 2000
filing date -
09/584,429
serial no -
In Force
status
Importance
Abstract
A method of forming a metal interconnect within a fluorinated silica glass dielectric layer while preventing outgassing from the fluorinated silica glass dielectric layer comprising the following steps. A semiconductor structure having a semiconductor device structure formed therein is provided. A metal line is formed over the semiconductor structure. The metal line being electrically connected with the semiconductor device structure. An insulating layer is formed over the semiconductor structure, covering the metal line. A fluorinated silica glass dielectric layer is formed over the insulating layer. The fluorinated silica glass dielectric layer is planarized to form a planarized fluorinated silica glass dielectric layer. The planarized fluorinated silica glass dielectric layer and the insulating layer are patterned to form a via opening to the metal line, and exposing portions of the patterned fluorinated silica glass dielectric layer within the via opening. The via opening is treated with a plasma selected from the group comprising an N-containing plasma, an H-containing plasma, and a combination thereof. A metal interconnect is then formed within the via opening.
First Claim
Related Publications
International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,643,407 Solving the poison via problem by adding N.sub.2 plasma treatment after via etching | 27 | 1994 | |
| 5,904,566 Reactive ion etch method for forming vias through nitrogenated silicon oxide layers | 33 | 1997 | |
| 5,970,376 Post via etch plasma treatment method for forming with attenuated lateral etching a residue free via through a silsesquioxane spin-on-glass (SOG) dielectric layer | 62 | 1997 | |
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| 6,008,118 Method of fabricating a barrier layer | 12 | 1998 | |
| 6,074,941 Method of forming a via with plasma treatment of SOG | 5 | 1998 | |
| 6,077,784 Chemical-mechanical polishing method | 28 | 1998 | |
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| 5,763,010 Thermal post-deposition treatment of halogen-doped films to improve film stability and reduce halogen migration to interconnect layers | 32 | 1996 | |
| 5,827,785 Method for improving film stability of fluorosilicate glass films | 43 | 1996 | |
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| 5,976,626 Semiconductor device and method of manufacturing thereof | 4 | 1996 | |
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| 6,008,120 Silicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabrication | 46 | 1998 | |
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| 5,244,535 Method of manufacturing a semiconductor device including plasma treatment of contact holes | 19 | 1992 | |