Comparator
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United States of America Patent
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-
May 15, 2001
Grant Date -
N/A
app pub date -
Oct 14, 1999
filing date -
Oct 14, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A 64-bit comparator includes a first stage for receiving a 64-bit number A and a 64-bit number B, and generating first output values. A second stage then receives the first output values from the first stage and outputs second output values, and a third stage receives the second output values from the second stage and outputs greater than, less than, and equivalent values. Thus, the comparator is faster in that it is implemented in three logic stages by making efficient use of compound dynamic gates.
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