Clocking technique for reducing sampling noise in an analog-to-digital converter
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 15, 2001
Grant Date -
N/A
app pub date -
Mar 8, 1999
filing date -
Mar 8, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method and apparatus are disclosed for improving the operation of an analog-to-digital converter ('ADC'). A separate 'clean' oscillator clock is to be used in combination with a 'noisy' ADC clock being regulated by a phase-locked-loop (PLL) circuit. The 'noisy' ADC clock drives the digital control logic and also turns on the sample signal for the purpose of sampling. The second clock, which has a substantially fixed (i.e., 'clean') frequency is used to generate a short pulse, the leading edge of which turns off the sample signal, thereby providing an improved sampling process with greater resolution. The interaction of the two clocks is controlled with digital logic circuitry.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully