Printed circuit board and method for wiring signal lines on the same
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United States of America Patent
Stats
-
May 15, 2001
Grant Date -
N/A
app pub date -
Dec 30, 1998
filing date -
Nov 7, 1998
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Disclosed are a printed circuit board and a method for wiring signal lines on the same. Connecting lines for electrically connecting chip select pins of a semiconductor chip, no connect pins and address designate pins, are formed on a PCB. In case of an unstack type, a pad is connected to chip select pin and no connect functioning pin of other semiconductor chip via a first signal line. In case of a stack type, another pad used with a pad is connected to a no connect functioning pin and a chip select pin of the corresponding semiconductor chip having no connection with the first signal line via a second signal line. According to the type of semiconductor chip, e.g. unstack or stack type, a second connecting pad selectively connecting by a first jumper having almost zero resistance value, is disposed between the first and the second signal lines. A first connecting pad is also disposed at the second signal line, the first pad is selectively connected by a second jumper having zero resistance value. Seven connecting pads are disposed on the PCB and an outer pad for transmitting an address signal is connected to three pads which are not disposed adjacently in series. Among the remained four connecting pads, three pads are connected to connecting lines connecting the respective pins of semiconductor chips by signal lines, and the rest is connected to a signal line by another signal line. According to the memory capacity of semiconductor chip, the spaces between the respective connecting pads are selectively connected by jumpers.
First Claim
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| HYUNDAI ELECTRONICS INDUSTRIES CO LTD | GYEONGGI DO SOUTH KOREA GYEONGGI-DO |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Lee, Jung Woo | Ich'on, KR | 129 | 639 |
| Suh, Young Suk | Kwach'on, KR | 4 | 77 |
| Yoon, Yong Sik | Ich'on, KR | 1 | 71 |
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Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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