Non volatile semiconductor, memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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May 15, 2001
Grant Date -
N/A
app pub date -
Mar 30, 2000
filing date -
Feb 16, 1998
priority date (Note) -
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Abstract
A nonvolatile semiconductor memory device having a plurality of memory cells. Each cell stores data and has a threshold voltage corresponding to the data. A controller controls a partial erase operation in response to a command. This operation includes selecting memory cells in two groups, storing the data in a data latch, writing erase data indicating an erase state, erasing data of selected cells and programming the data stored in the data latch to selected memory cells and programming the erased data to selected memory cells.
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