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Abstract

The present invention relates to a memory interface controller for a data transmission system. A memory interface controller is capable of randomly accessing a memory using an associative memory and variably processing data using an extended memory. There is provided a memory interface controller which includes a control logic unit for selectively outputting signals; a comparand register for storing a sequence number; an associative memory for outputting a match address; a priority address encoder for outputting a priority match address; an external memory controller for outputting an empty address of the associative memory; an external tended memory controller for outputting a priority empty address; and an extended memory address and control signal generator for generating an address and a control signal (enable/read/write).

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First Claim