Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions
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United States of America Patent
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May 15, 2001
Grant Date -
N/A
app pub date -
Mar 31, 1998
filing date -
Mar 31, 1998
priority date (Note) -
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Abstract
A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
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