Multi-bit memory device having error check and correction circuit and method for checking and correcting data errors therein
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United States of America Patent
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May 15, 2001
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N/A
app pub date -
Dec 18, 1998
filing date -
Dec 31, 1997
priority date (Note) -
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Abstract
An integrated circuit multi-bit memory device incorporating an error check and correction (ECC) technique is provided. In the error correction, two or more groups of parity bits corresponding to a data word of the multi-bit memory device are programmed therein. The groups are classified by the number of bits per cell. Error bits in a memory data word are checked sequentially by the group, and the checked error bits are also corrected sequentially by the group, thereby preventing the device failure due to two or more errors in a data word of the multi-bit memory device.
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