Power bus and method for generating power slits therein
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United States of America Patent
Stats
-
May 15, 2001
Grant Date -
N/A
app pub date -
Mar 16, 1999
filing date -
Feb 10, 1992
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.
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