Controlled impedance bus and method for a computer system
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United States of America Patent
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May 22, 2001
Grant Date -
N/A
app pub date -
Feb 4, 1999
filing date -
Feb 4, 1999
priority date (Note) -
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Abstract
A multi-layer circuit substrate having an integral bus portion includes a dielectric substrate having a first device signal layer formed on a first side thereof and a second device signal layer formed on a second side thereof. The first and second device signal layers are each patterned to include at least one bus reference plane. A device reference plane layer is disposed between the first and second device signal layers in the dielectric substrate. The device reference plane layer is patterned to include a plurality of guard bands and a bus signal trace between at least two of the guard bands.
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