Method for simultaneously programming plural flash memories having invalid blocks
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United States of America Patent
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May 22, 2001
Grant Date -
N/A
app pub date -
Apr 26, 2000
filing date -
Apr 27, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
Disclosed is a method for programming flash memories, each of which has a memory cell array divided into plural blocks. Each of the blocks is associated with block status information indicating whether it is valid. According to the programming method of the present invention, first, a parallel-programming process is performed for valid blocks of all of the flash memories. Then, a serial-programming process is performed for flash memories having invalid blocks. This enables the time required for programming flash memories with one or more invalid blocks to be reduced.
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