Importance

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Abstract

The present invention relates to a fail-safe timing circuit and on-delay circuit which does not produce an erroneous output where the delay time is shortened, due to a fault. The timing circuit comprises: an oscillation circuit (11) which produces a timing output from a cathode terminal of a PUT after a predetermined time lapse from input of an input signal (V.sub.IN); and a monitoring circuit (12) for monitoring for the normalcy of the oscillation circuit (11). Moreover the on-delay circuit comprises a self hold circuit (13) with an output signal (Vo) generated from the monitoring circuit (12) only when the normalcy of the oscillation circuit (11) is verified by generation of a falling signal of a cathode terminal voltage of the oscillation circuit (11), input to a second terminal (b), and the input signal (V.sub.IN) input to a first terminal (a), which produces an output signal only when the two input signals are both at a higher level than a power source potential.

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First Claim