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Abstract

An incoming memory address signal is compared and matched with static signals provided by a fuse array that represents an address of a defective memory column that is being replaced by a redundant memory column in a memory chip. Each section of a memory is provided with a redundant memory column. Each redundant column of the memory is connected to a separate redundant-column sense amp that is activated by a memory section-select signal in combination with a BIGHIT signal. The BIGHIT signal indicates that the memory chip has received an address of a defective memory column. All of the output terminals of the redundant column senseamps are connected in common to a redundant internal data bus RDINTDB. A defective-column-address detector circuit compares an incoming multi-bit memory address signal to an address of a defective memory column and provides an address-hit signal ADDHIT if a match occurs therebetween. A BIGHIT circuit combines the ADDHIT signals for all of the memory sections to provide the BIGHIT signal when any ADDHIT signal is present. A 2:1 multiplexer connects a redundant senseamp or a normal senseamp to a chip output terminal.

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First Claim