Importance

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Abstract

A synchronous type dynamic random access memory (SDRAM) includes a memory cell array section having an address decoder section and a sense amplifier section, a power down signal generating section, a control signal generating section and an accessing section. The power down signal generating section generates a first power down signal and a second power down signal based on a clock enable signal, an external clock signal, a signal specific to the SDRAM and a write burst signal. The first power down signal is inactive during a predetermined time period synchronous with the specific signal, and the second power down signal is inactive during the predetermined time period and during a time period during which the write burst signal is supplied. The control signal generating section generates a control signal based on a command signal when the first power down signal is inactive. The accessing section accesses the memory cell array section based on an external address signal and an external data signal in response to the control signal when the first power down signal or the second power down signals is inactive.

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First Claim