Buffer memory with parallel data and transfer instruction buffering
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United States of America Patent
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May 29, 2001
Grant Date -
N/A
app pub date -
May 22, 1998
filing date -
May 14, 1998
priority date (Note) -
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Abstract
A high speed buffer memory interface for connecting network and host devices provides dual paths of buffering where data travels via an input buffer or output buffer and instructions about the transfer of that data travel via a receive buffer and command buffer. The microprocessor reads instructions from the receive buffer placed there by the network interface circuitry and writes instructions to the command buffer to be read by the network interface circuitry without need to precisely synchronize with the input and network interface circuitry as would require time consuming, interrupt-type transactions.
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