Stacked package of semiconductor package units via direct connection between leads and stacking method therefor
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United States of America Patent
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Jun 5, 2001
Grant Date -
N/A
app pub date -
Jan 15, 1999
filing date -
Jul 23, 1998
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A stacked package of semiconductor package units and a stacking method thereof through direct connection between leads to effectively stack a number of semiconductor packages are provided, in which a lead deformation process of straightening leads of an upper semiconductor package is performed to form a stacked package, and predetermined leads of the semiconductor packages above a lower semiconductor package being a conventional standard semiconductor package are directly connected, considering an external and internal electrical connection state of a package. The semiconductor packages are used for forming a stacked package through directly connecting predetermined leads of the semiconductor packages, in which a connection state between a CS lead of an operation select-function for activating the operation of a predetermined semiconductor package and any one NC lead of a number of NC leads which are not connected is changed externally and internally in a package. The volume of the stacked package is reduced half to thereby minimize a surface mounting area of the stacked package. A stacking processes are simplified by solving the conventional complicated problems. Also, one testing equipment can test semiconductor packages which are used for the stacked packages of the present invention, because the outside shape of the unit packages is identical prior to the lead deformation. Thus, costs are not only saved but also a number of semiconductor packages can be efficiently stacked.
First Claim
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| RECO INC | 102-602 #88 SINWON-RO YEONGTONG-GU SUWON-SI GYEONGGI-DO 443-734 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Kang, Kyung Suk | A-302, Changmi-oneroom, 331, Yangji-ri, Yangji-myon, Yongin-city Kyungki-do, KR | 4 | 31 |
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|---|
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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