Method of etching a wafer layer using a sacrificial wall to form vertical sidewall

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United States of America Patent

PATENT NO 6242363
SERIAL NO

09372700

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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One embodiment of the invention is a method for forming a raised structure on a semiconductor wafer. In the method, a patterned masking layer is formed over a wafer layer. The patterned masking layer typically includes a first mask covering a first region of the wafer layer and at least one side mask adjacent to the first mask, covering a side region of the wafer layer. After forming the patterned masking layer, exposed portions of the wafer layer adjacent the masks are removed using the patterned masking layer. This leaves a first raised structure (relative to an adjacent removed area) in the first substrate region and a sacrificial raised structure in the side region adjacent the first raised structure. After removing the exposed portions of the wafer layer, the sacrificial raised structure is selectively removed while leaving the first raised structure intact. The sacrificial raised structure and overlying side mask typically reduce the area of the wafer layer which would otherwise be exposed during the removal. This facilitates the formation of the vertical sidewall on the raised structure.

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Patent Owner(s)

  • ADC TELECOMMUNICATIONS, INC.;COMMSCOPE TECHNOLOGIES LLC

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Zhang, Nan Eden Prairie, MN 419 2040

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