Embedded memory block with FIFO mode for programmable logic device
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United States of America Patent
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Jun 5, 2001
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N/A
app pub date -
Aug 5, 1999
filing date -
Apr 15, 1996
priority date (Note) -
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Abstract
An programmable logic device has an enhanced embedded array block for the efficient implementation of logic functions including a random access memory and a first-in, first-out memory. A read address register and a write address register are implemented within the embedded array block. The address registers are coupled with a memory array in the embedded array block without using a resources from a programmable interconnect scheme. The first-in, first-out memory may operate as a dual-port FIFO, without cycle-sharing on the interconnect lines.
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